add initial labs
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labs/lab_w2/Clock.c
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169
labs/lab_w2/Clock.c
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// Clock.c
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// Runs on the MSP432
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// Daniel and Jonathan Valvano
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// February 23, 2017
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/* This example accompanies the book
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"Embedded Systems: Introduction to Robotics,
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Jonathan W. Valvano, ISBN: 9781074544300, copyright (c) 2019
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For more information about my classes, my research, and my books, see
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http://users.ece.utexas.edu/~valvano/
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Simplified BSD License (FreeBSD License)
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Copyright (c) 2019, Jonathan Valvano, All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are
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those of the authors and should not be interpreted as representing official
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policies, either expressed or implied, of the FreeBSD Project.
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*/
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#include <stdint.h>
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#include "msp.h"
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uint32_t ClockFrequency = 3000000; // cycles/second
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//static uint32_t SubsystemFrequency = 3000000; // cycles/second
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// ------------Clock_InitFastest------------
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// Configure the system clock to run at the fastest
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// and most accurate settings. For example, if the
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// LaunchPad has a crystal, it should be used here.
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// Call BSP_Clock_GetFreq() to get the current system
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// clock frequency for the LaunchPad.
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// Input: none
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// Output: none
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uint32_t Prewait = 0; // loops between BSP_Clock_InitFastest() called and PCM idle (expect 0)
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uint32_t CPMwait = 0; // loops between Power Active Mode Request and Current Power Mode matching requested mode (expect small)
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uint32_t Postwait = 0; // loops between Current Power Mode matching requested mode and PCM module idle (expect about 0)
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uint32_t IFlags = 0; // non-zero if transition is invalid
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uint32_t Crystalstable = 0; // loops before the crystal stabilizes (expect small)
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void Clock_Init48MHz(void){
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// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
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while(PCM->CTL1&0x00000100){
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// while(PCMCTL1&0x00000100){
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Prewait = Prewait + 1;
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if(Prewait >= 100000){
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return; // time out error
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}
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}
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// request power active mode LDO VCORE1 to support the 48 MHz frequency
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PCM->CTL0 = (PCM->CTL0&~0xFFFF000F) | // clear PCMKEY bit field and AMR bit field
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// PCMCTL0 = (PCMCTL0&~0xFFFF000F) | // clear PCMKEY bit field and AMR bit field
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0x695A0000 | // write the proper PCM key to unlock write access
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0x00000001; // request power active mode LDO VCORE1
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// check if the transition is invalid (see Figure 7-3 on p344 of datasheet)
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if(PCM->IFG&0x00000004){
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IFlags = PCM->IFG; // bit 2 set on active mode transition invalid; bits 1-0 are for LPM-related errors; bit 6 is for DC-DC-related error
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PCM->CLRIFG = 0x00000004; // clear the transition invalid flag
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// to do: look at CPM bit field in PCMCTL0, figure out what mode you're in, and step through the chart to transition to the mode you want
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// or be lazy and do nothing; this should work out of reset at least, but it WILL NOT work if Clock_Int32kHz() or Clock_InitLowPower() has been called
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return;
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}
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// wait for the CPM (Current Power Mode) bit field to reflect a change to active mode LDO VCORE1
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while((PCM->CTL0&0x00003F00) != 0x00000100){
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CPMwait = CPMwait + 1;
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if(CPMwait >= 500000){
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return; // time out error
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}
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}
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// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
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while(PCM->CTL1&0x00000100){
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Postwait = Postwait + 1;
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if(Postwait >= 100000){
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return; // time out error
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}
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}
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// initialize PJ.3 and PJ.2 and make them HFXT (PJ.3 built-in 48 MHz crystal out; PJ.2 built-in 48 MHz crystal in)
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PJ->SEL0 |= 0x0C;
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PJ->SEL1 &= ~0x0C; // configure built-in 48 MHz crystal for HFXT operation
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// PJDIR |= 0x08; // make PJ.3 HFXTOUT (unnecessary)
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// PJDIR &= ~0x04; // make PJ.2 HFXTIN (unnecessary)
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CS->KEY = 0x695A; // unlock CS module for register access
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CS->CTL2 = (CS->CTL2&~0x00700000) | // clear HFXTFREQ bit field
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0x00600000 | // configure for 48 MHz external crystal
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0x00010000 | // HFXT oscillator drive selection for crystals >4 MHz
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0x01000000; // enable HFXT
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CS->CTL2 &= ~0x02000000; // disable high-frequency crystal bypass
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// wait for the HFXT clock to stabilize
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while(CS->IFG&0x00000002){
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CS->CLRIFG = 0x00000002; // clear the HFXT oscillator interrupt flag
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Crystalstable = Crystalstable + 1;
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if(Crystalstable > 100000){
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return; // time out error
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}
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}
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// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 0
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FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL&~0x0000F000)|FLCTL_BANK0_RDCTL_WAIT_2;
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// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 1
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FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL&~0x0000F000)|FLCTL_BANK1_RDCTL_WAIT_2;
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CS->CTL1 = 0x20000000 | // configure for SMCLK divider /4
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0x00100000 | // configure for HSMCLK divider /2
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0x00000200 | // configure for ACLK sourced from REFOCLK
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0x00000050 | // configure for SMCLK and HSMCLK sourced from HFXTCLK
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0x00000005; // configure for MCLK sourced from HFXTCLK
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CS->KEY = 0; // lock CS module from unintended access
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ClockFrequency = 48000000;
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// SubsystemFrequency = 12000000;
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}
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// ------------Clock_GetFreq------------
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// Return the current system clock frequency for the
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// LaunchPad.
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// Input: none
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// Output: system clock frequency in cycles/second
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uint32_t Clock_GetFreq(void){
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return ClockFrequency;
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}
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// delay function
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// which delays about 6*ulCount cycles
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// ulCount=8000 => 1ms = (8000 loops)*(6 cycles/loop)*(20.83 ns/cycle)
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//Code Composer Studio Code
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void delay(unsigned long ulCount){
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__asm ( "pdloop: subs r0, #1\n"
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" bne pdloop\n");
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}
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// ------------Clock_Delay1us------------
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// Simple delay function which delays about n microseconds.
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// Inputs: n, number of us to wait
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// Outputs: none
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void Clock_Delay1us(uint32_t n){
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n = (382*n)/100;; // 1 us, tuned at 48 MHz
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while(n){
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n--;
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}
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}
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// ------------Clock_Delay1ms------------
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// Simple delay function which delays about n milliseconds.
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// Inputs: n, number of msec to wait
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// Outputs: none
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void Clock_Delay1ms(uint32_t n){
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while(n){
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delay(ClockFrequency/9162); // 1 msec, tuned at 48 MHz
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n--;
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}
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}
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