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+# Interrupts (1)
+
+## ARMv7-M Interrupt Handling
+
+* 1 NMI supported
+* Up to 511(496 external, 15 internal) prioritizable interrupts/exceptions supported
+* NVIC is highly coupled with processor
+
+## ISR Vector Table
+
+
+## Interrupt Handling Process
+
+1. start `main`
+   1. if interrupt signal detects
+   2. processor stops `main`
+   3. auto stacking `PUSH {r0 ... r3, r12, lr, pc, psr}`
+2. `pc = memory address of SysTick_Handler`
+3. execute ISR
+4. Interrupt Returns. Active bits will be cleared
+   1. Auto unstacking `POP {r0 ... r3, r12, lr, pc, psr}`
+5. continue `main`
+
+### Stacking and Unstacking
+
+When Interrupts, it automatically **stacking** `r0`, `r1`, `r2`, `r3`, `r12`, `lr`, `pc`, `psr`.
+
+When Exiting Interrupts, it automatically **unstacking** `r0`, `r1`, `r2`, `r3`, `r12`, `lr`, `pc`, `psr`.
+
+It is done by hardware, not software.
+
+## Exception Exits
+