# Memory

## Default Memory Access Permissions

The Cortex-M3 memory map has a default configuration for memory access permissions
Default memory access permission is used when either:
* No MPU is present
* MPU is present but disabled
Otherwise MPU will determine
When a memory access is blocked the fault exception takes place immediately.

```python { cmd matplotlib hide }

import pymupdf

from PIL import Image

doc = pymupdf.open("./pdf/L4.pdf")

pix = doc[12].get_pixmap()
img = Image.frombytes("RGB", [pix.width, pix.height], pix.samples)
plt.axis('off')
plt.subplots_adjust(left=0, right=1, top=1, bottom=0)
plt.imshow(img)

plt.show()

```

## MPU(Memory Protection Unit)

MPU

Regions can be overlapped only in ARMv7

## Bit-Band Operations

it allows a single load/store opertation to access a **single data bit**.

Bit-band regions:
* The first 1MB of the SRAM region
* The first 1MB of theperipheral region

They can be accessed via a separate memory region called the bit-band alias.

Bit-Banding done transparently by **bus matrix**.

### Write to Bit-Band Alias

* Without Bit-Band:
```armasm
LDR   R0, =0x20000000 ; Setup address
LDR   R1, [R0]        ; Read
ORR.W R1, #0x4        ; Modify bit
STR   R1, [R0]        ; Write back result
```

* With Bit-Band:
```armasm
LDR   R0, =0x22000008 ; Setup address
MOV   R1, #1          ; Setup data
STR   R1, [R0]        ; Write
```


### Read from the Bit-Band Alias

To get bit 2 in word data in address `0x20000000`:
* Without
```armasm
LDR    R0, =0x20000000 ; Setup address
LDR    R1, [R0]        ; Read
UBFX.W R1, R1, #2, #1  ; Extract Bit[2]
```

* With
```armasm
LDR R0, = 0x22000008 ; Setup address
LDR R1, [R0]         ; Read
```

### Advantages of using bit-band ops

* Faster bit operations with fewer instructions
* Prevent a **race condition** problem in bit modification


### Usecase in C

* There is no native support of bit-band ops in most C compilers
  * The simplest solution is to separately declare the address and the bit-band alias of a memory location

```c
#define DEVICE_REGO      *((volatile unsigned long *) 0x40000000)
#define DEVICE REGO_BIT0 *((volatile unsigned long *) 0x42000000)
#define DEVICE REGO_BIT1 *((volatile unsigned long *) 0x42000004)
```


## Unaligned Transfers

Coretex-M3 optionally supports unaligned transfers on single accesses.
Data memory accesses can be defined as aligned or unaligned.

Unaligned transfers are converted into multiple aligned transfers by the processor's bus interface unit:
* transparent to application programmers
* it takes more clock cycles for a single data access

Limitations:
* Not supported in load/store multiple instructions
* Stack operations (PUSH/POP) must be aligned
* Exclusive access must be aligned
* Unaligned transfers are not supported in bit-band ops